1. Field of the Invention
The present invention relates to an information reproduction apparatus and an information reproduction method, and more particularly relates to an information reproduction apparatus and an information reproduction method which can obtain a low determination error rate, even when a reproduction signal has a nonlinear distortion.
2. Description of Related Art
In recent years, the recording density of optical disc recording/reproducing apparatuses is increasing. In such apparatuses having high density, the PRML (Partial-Response Maximum-Likelihood) signal process is adopted in the signal reproduction process, in many cases. The PRML signal process carries out a waveform equalization corresponding to properties of the recording/reproducing system, and determines a data based on the maximum-likelihood detection through a Viterbi detector and can attain a low error rate even for a reproduction signal in which an inter-code interference is large. However, in the PRML signal process, there is a case that the original performance of the PRML is not sufficiently provided because of the nonlinear distortion of the reproduction signal that is generated in association with the marks formed in high density.
At first, the PRML signal process is described with reference to FIGS. 1, 2, 3A and 3B. FIG. 1 is a state transition diagram of a reproduction signal sequence that is sampled at a channel bit interval, when as a modulation code, a code in which a minimum code inversion interval is 2 is used to carry out a recording/reproducing operation and then the reproduction signal is PR (a, b, b, a) equalized. States S0 to S5 indicate states determined from three channel bits that include the channel bits immediately before and immediately after. The states S0, S1 and S5 indicate the states in which current channel bit is [0]. The states S2, S3 and S4 indicate that the current channel bit is [1]. Symbols r0 to r6 indicated on arrow marks that represent shifts between the states are the expectation values of the reproduction signals corresponding to the respective shifts. The expectation values r0 to r6 are represented by the equations (1) to (7), respectively, in the case of PR (a, b, b, a).r0=−b−a   (1)r1=−b   (2)r2=−b+a   (3)r3=0   (4)r4=b−a   (5)r5=b   (6)r6=b+a   (7)
FIG. 2 is a trellis diagram obtained by developing the state transition diagram in FIG. 1 in the time axis direction. In the trellis diagram, considering the combinations of all paths generated through any state from any state corresponds to consider all bit sequences in which the constraints of the signs are considered. In the PRML signal process, ideal waveforms that are expected for all the paths included in the trellis diagram are compared with the reproduction signal actually reproduced from an optical disc. Then, in the PRML signal process, the path having the ideal waveform that is closest to the reproduction signal is selected to specify the most probable channel bit sequence in accordance with the path.
With reference to the trellis diagram in FIG. 2, two arrow marks merge in each of the states S0, S1, S3 and S4 at any time. The Viterbi detector used in the PRML signal process compares indexes that indicate the respective closenesses between the ideal waveforms expected corresponding to the paths and the waveform of the reproduction signal, for the states S0, S1, S3 and S4 in which plurality of arrow marks merge as mentioned above. Then, the Viterbi detector proceeds with the path selection by leaving the path, which is the closest to the ideal waveform, one by one, for each state. As the Viterbi detector proceeds with the path selection, the six paths equal to the number of the states are left at a certain time. The number of the survivor paths is decreased with the passage of time. Then, the six paths become coincident at some time. The Viterbi detector sequentially outputs only the range in which the paths are coincident. In this way, the PRML signal process can obtain the most probable channel bit sequence from the reproduction signal. For the index indicating the closeness between an ideal waveform and a reproduction signal waveform, a path metric corresponding to the value obtained by squaring the Euclidean distance between both of the waveforms is used. The path metric is obtained by totaling the branch metric obtained for each arrow mark for coupling the states along the path.
FIGS. 3A and 3B show a configuration example of a Viterbi detector. With reference to FIGS. 3A and 3B, the Viterbi detector contains a branch metric calculation circuit 101, a path metric update circuit 102, a path metric comparison circuit 103, a path metric selection circuit 104, a minimum value determination circuit 105 and a path memory 106.
The branch metric calculation circuit 101 receives an equalization signal obtained by performing an equalization of a waveform on the sampled reproduction signal sequence. The branch metric calculation circuit 101 includes a plurality of sub blocks (BM0 to BM6). The respective sub blocks (BM0 to BM6) calculate a blanch metric Bn[t] from the equation (8), in accordance with a sample value y[t] of the equalization signal and the expectation values r0 to r6.Bn[t]=rn2−2rny[t](n=0, - - - 6)   (8)
The expectation value rn used in the sub block BMn is a fixed value. Thus, when a and b have a relation of an integer ratio, the branch metric calculation circuit 101 can be realized by using a few adders without using a multiplier. For example, when a is 1 and b is 2, the expectation value rn becomes an integer between −3 and 3. Thus, the first term of Bn[t] is a constant, and the second term is represented by the multiplication of a constant between 6 and −6 and y[t]. When the value is represented by the two's complement, the two times is represented by a 1-bit shift, the four times is represented by a 2-bit shift, and a value of six times is represented by the addition of the value of two times and the value of four times. Also, the minus number is obtained only by inverting the polarities of all bits. Thus, the circuit quantity required to obtain the Bn[t] is the two adders and the circuits for inverting the polarities of all the bits.
The path metric update circuit 102 includes a plurality of adders (Add00, Add51, Add01, Add52, Add43, Add13, Add24, Add35, Add25 and Add36) as sub blocks. Each adder calculates a candidate of the path metric at a time t, in accordance with the value of the path metric Pm[t−1] immediately before and corresponding to the state Sm (m=0, - - - 5) and the branch metric Bn[t] and outputs it. For example, the adder Addmn in a sub block functions to calculate the path metric of the path, which passes through the state Sm at of a time t−1 and further passes through the arrow mark of the expectation value rn and then transitions to a next state.
In other words, exemplifying a case of m=0, the path metric update circuit 102 calculates candidates of a path metric correlated to a third state S3 at time t based on a plurality of branch metrics, the first path metric P0[t−1] correlated to a first state S0 at time t−1 and the second path metric P5[t−1] correlated to a second state S5 at time t−1. Assuming that such candidates is represented as a third path metric and a fourth path metric. The third path metric can be calculated from a first branch metric B0[t] included in a plurality of branch metrics Bn[t] (n=0, . . . , 6) and the first path metric P0[t−1]. The fourth path metric can be calculated from a second branch metric B1[t] and the second path metric P5[t−1].
The path metric comparison circuit 103 includes a plurality of comparators (Cmp0, Cmp1, Cmp3 and Cmp4) as sub blocks. Each of the plurality of comparators compares the magnitudes of the path metrics outputted by the path metric update circuit 102, in a state in which a plurality of paths merge, and outputs a selection signal indicating the comparison result.
The path metric selection circuit 104 includes a plurality of selectors (Se10, Se11, Se13 and Se14) and a plurality of registers (PM0, PM1, PM2, PM3, PM4 and PM5) as sub blocks. Each of the plurality of selectors selects the value of the path metric that is determined to be smaller, in accordance with the selection signal received from the path metric comparison circuit 103. Each of the plurality of registers updates and holds the path metric Pn[t] of the time t corresponding to each of the states. In the aforementioned case, the path metric selection circuit 104 selects smaller one of the third path metric and the fourth path metric and hold the selected one with the third state at time t. The path metric update circuit 102, the path metric comparison circuit 103 and the path metric selection circuit 104 are the main elements of the Viterbi detector that are mainly composed of adders, comparators and selectors, respectively, and is referred to as the ACS (Add-Compare-Select) circuit, in many cases. The ACS circuit in FIG. 3 updates the path metric at any time t, in accordance with the equations (9) to (14).P0[t]=min(P0[t−1]+B0[t], P5[t−1]+B1[t])   (9)P1[t]=min(P0[t−1]+B1[t], P5[t−1]+B2[t])   (10)P2[t]=P1[t−1]+B3[t]  (11)P3[t]=min(P2[t−1]+B5[t], P3[t−1]+B6[t])   (12)P4[t]=min(P2[t−1]+B4[t], P3[t−1]+B5[t])   (13)P5[t]=P4[t−1]+B3[t]  (14)
The symbol min (A, B) represented in the equations indicates the process of selecting the smaller value from A and B. The numbers of arrow marks directed to the states S2 and S5 are respectively one. Thus, the min (A, B) is not used to update P2[t] and P5[t].
The minimum value determination circuit 105 compares P0[t] to P5[t] that indicate the path metrics in the respective states and determines the path metric having the smallest value. Then, the minimum value determination circuit 105 outputs the determination result to the path memory 106.
The path memory 106 includes a plurality of registers (the rectangular blocks on the drawing) and a plurality of selectors (the trapezoidal blocks on the drawing). The path memory 106 holds the path selected by the path metric selection circuit 104, as path information represented by the channel bit, in accordance with the selection signal outputted by the path metric comparison circuit 103. The register group on the lowest stage in the path memory 106 in FIG. 3 holds the path information corresponding to the path which traces back to the state S0. The register groups thereon correspond to the paths, which trace back to the state S1, state S5, state S2, state S4 and state S3, in the order from the bottom. Each register stores one bit in the channel bit of the corresponding path, and each bit is sent to the column to the right one at a time with the passage of time. At the time t, the register of the column of the left end in the register group in each stage holds the channel bit of the time t. Then, the column immediately to the right holds the channel bit of the time t−1, and the next column of the right thereof holds the channel bit of the time t−2. When the path memory 106 contains the registers of about 30 columns, a same value is held in the registers of all the stages at a high probability, in the column of the right end. It is possible to obtain the result of the Viterbi detection even by selecting any one stage from the column of the right end of the path memory 106 and outputting one bit at a time. In the example in FIG. 3B, the selector for selecting the path from which the channel bit is taken out from the paths which respectively trace back from the states S0 to S5, so as to be able to output more probable value, even when the value of the channel bit contained in the register of the column of the right end is different depending on the stage. The selector of the right end of the path memory 106 selects and outputs the channel bit of the stage corresponding to the state in which the path metric is minimum at each time, in accordance with the determination result of the minimum value determination circuit 105.
In Japanese Patent Application Publication JP-A-Heisei, 11-330986, which is referred to as the patent document 1 below, techniques related to the PRML signal process is disclosed. The patent document 1 proposes an apparatus for correcting the expectation value used to calculate the branch metric, on the basis of an offset amount and a nonlinear distortion quantity, which depend on the property of a recording medium and the property of a reproducing system. The expectation value rn is corrected in response to the trend of the distortion generated in the reproduction signal. Consequently, the path metric for each path is accurately obtained, and determination errors can be reduced.
Japanese Patent Application Publication JP-P 2008-262611A, which is referred to as the patent document 2 below, discloses a decoding method in which an offset is added to the path metric corresponding to a predetermined path. The path metric difference between the ideal waveforms corresponding to the merging two paths has a value that is different depending on the path. For example, in an example of PR (1, 2, 2, 1), in the trellis diagram in FIG. 2, the path metric difference is 10 between the ideal waveforms, which correspond to the two paths S0→S1→S2→S3→S3 and S0→S0→S1→S2→S3 that pass through the state S0 at a time t−4 and merge at the state S3 at a time t. The path metric difference is 12 between the ideal waveforms, which correspond to the two paths S0→S0→S0→S0→S0→S0 and S0→S1→S2→S4→S5→S0 that pass through the state S0 at a time t−5 and merge at the state S0 at the time t. In the patent document 2, as indicated in the two paths that pass through the state S0 at the time t−5 and merge at the state S0 at the time t, the process is carried out to add the offset to the path metric, for the paths in which the expectation value of the path metric difference does not become minimum. The process of adding the offset to the path metric can correct a deviation appearing in the path metric, when the distortion exists in the reproduction signal having a large difference from the path metric obtained by another pattern, such as a reproduction signal obtained from a long mark. Thus, the effect of reducing the determination error can be expected.